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Our portfolio spans across multiple disciplines, including engineering, technology, medicine, and social sciences, providing cutting-edge insights for researchers, academics, and professionals.  We work with experts and thought leaders to deliver timely, relevant, and peer-reviewed resources. Our reputation for quality and integrity ensures that River Publishers is a trusted partner in academic and professional research.\u003C/p>","2024-12-17T14:49:40.685Z","2025-01-10T19:01:28.716Z","2024-12-17T14:49:42.364Z","319",{"id":1496,"name":1497,"alternativeText":16,"caption":16,"width":1498,"height":1499,"formats":1500,"hash":1524,"ext":19,"mime":20,"size":1525,"url":1526,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1527,"updatedAt":1527},246,"ISCAS_2025_Patron-Logos_River Publishers.png",2148,1004,{"large":1501,"small":1507,"medium":1513,"thumbnail":1518},{"ext":19,"url":1502,"hash":1503,"mime":20,"name":1504,"path":16,"size":1505,"width":787,"height":1506},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/large_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48.png","large_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48","large_ISCAS_2025_Patron-Logos_River Publishers.png",51.68,467,{"ext":19,"url":1508,"hash":1509,"mime":20,"name":1510,"path":16,"size":1511,"width":736,"height":1512},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/small_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48.png","small_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48","small_ISCAS_2025_Patron-Logos_River Publishers.png",25.02,234,{"ext":19,"url":1514,"hash":1515,"mime":20,"name":1516,"path":16,"size":335,"width":743,"height":1517},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/medium_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48.png","medium_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48","medium_ISCAS_2025_Patron-Logos_River Publishers.png",351,{"ext":19,"url":1519,"hash":1520,"mime":20,"name":1521,"path":16,"size":1522,"width":805,"height":1523},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48.png","thumbnail_ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48","thumbnail_ISCAS_2025_Patron-Logos_River Publishers.png",12.53,115,"ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48",19.18,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/ISCAS_2025_Patron_Logos_River_Publishers_1e9b781b48.png","2024-12-17T14:49:30.859Z",{"id":1290,"variation":757,"button":1529},[1530],{"id":1531,"label":761,"size":762,"color":763,"style":16,"icon":764,"iconPosition":765,"url":1532,"newWindow":8,"downloadable":16,"shape":16},101,"http://www.riverpublishers.com/","-198",{"id":620,"name":1535,"description":1536,"createdAt":1537,"updatedAt":1538,"publishedAt":1539,"url_path_id":1540,"logo":1541,"website":1573,"url_path":1578},"Cirrus Logic","\u003Cp style=\"text-align:justify;\">Founded in 1984 in Silicon Valley, Cirrus Logic is a leader in low-power, high-precision, mixed-signal processing solutions. Leveraging a broad portfolio of hardware, software and proprietary algorithms, Cirrus Logic excels at developing IP-rich solutions that create innovative user experiences for the world’s top mobile and consumer applications. Cirrus Logic has approximately 3,940 issued and pending patents worldwide and counting.\u003C/p>\u003Cp style=\"text-align:justify;\">Cirrus Logic is a recognized leader in low-power, high-precision, mixed-signal audio solutions that include products such as smart codecs, audio DSPs, boosted amplifiers, haptic and sensing ICs, camera controllers, battery and power ICs, analog-to-digital converters (“ADCs”), digital-to-analog converters (“DACs”), codecs that integrate ADCs and DACs into a single IC, digital interface ICs and power stages. Our products are used in a wide array of consumer applications, including smartphones, tablets, laptops, digital headsets, wearables, Bluetooth speakers, and smart home accessories.\u003C/p>","2024-12-18T13:52:37.376Z","2024-12-18T18:34:48.482Z","2024-12-18T13:52:39.678Z","320",{"id":1542,"name":1543,"alternativeText":16,"caption":16,"width":1544,"height":1545,"formats":1546,"hash":1569,"ext":19,"mime":20,"size":1570,"url":1571,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1572,"updatedAt":1572},249,"ISCAS_2025_Patron-Logos_cirrus-logic.png",1491,264,{"large":1547,"small":1553,"medium":1558,"thumbnail":1564},{"ext":19,"url":1548,"hash":1549,"mime":20,"name":1550,"path":16,"size":1551,"width":787,"height":1552},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/large_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35.png","large_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35","large_ISCAS_2025_Patron-Logos_cirrus-logic.png",35.81,177,{"ext":19,"url":1554,"hash":1555,"mime":20,"name":1556,"path":16,"size":1557,"width":736,"height":860},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/small_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35.png","small_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35","small_ISCAS_2025_Patron-Logos_cirrus-logic.png",15.47,{"ext":19,"url":1559,"hash":1560,"mime":20,"name":1561,"path":16,"size":1562,"width":743,"height":1563},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/medium_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35.png","medium_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35","medium_ISCAS_2025_Patron-Logos_cirrus-logic.png",25.11,133,{"ext":19,"url":1565,"hash":1566,"mime":20,"name":1567,"path":16,"size":1568,"width":805,"height":160},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35.png","thumbnail_ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35","thumbnail_ISCAS_2025_Patron-Logos_cirrus-logic.png",6.7,"ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35",8.8,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/ISCAS_2025_Patron_Logos_cirrus_logic_7e45301a35.png","2024-12-18T13:52:21.065Z",{"id":1251,"variation":757,"button":1574},[1575],{"id":1576,"label":761,"size":762,"color":763,"style":16,"icon":764,"iconPosition":765,"url":1577,"newWindow":8,"downloadable":16,"shape":16},102,"http://cirrus.com/","-199",{"id":259,"name":1580,"description":1581,"createdAt":1582,"updatedAt":1583,"publishedAt":1584,"url_path_id":1585,"logo":1586,"website":1607,"url_path":1612},"Applied Materials","\u003Cp style=\"text-align:justify;\">We are the leader in materials engineering solutions used to produce virtually every new chip and advanced display in the world. Our expertise in modifying materials at atomic levels and on an industrial scale enables customers to transform possibilities into reality. At Applied Materials, our innovations Make Possible® a Better Future.\u003C/p>","2025-01-14T21:18:16.987Z","2025-01-14T21:18:19.761Z","2025-01-14T21:18:19.748Z","345",{"id":1587,"name":1588,"alternativeText":16,"caption":16,"width":1589,"height":1590,"formats":1591,"hash":1603,"ext":781,"mime":784,"size":1604,"url":1605,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1606,"updatedAt":1606},261,"AppliedWebLogoEnglish102021.jpg",525,187,{"small":1592,"thumbnail":1597},{"ext":781,"url":1593,"hash":1594,"mime":784,"name":1595,"path":16,"size":1596,"width":736,"height":1348},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/small_Applied_Web_Logo_English102021_cd0b2bb837.jpg","small_Applied_Web_Logo_English102021_cd0b2bb837","small_AppliedWebLogoEnglish102021.jpg",11.68,{"ext":781,"url":1598,"hash":1599,"mime":784,"name":1600,"path":16,"size":1601,"width":805,"height":1602},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_Applied_Web_Logo_English102021_cd0b2bb837.jpg","thumbnail_Applied_Web_Logo_English102021_cd0b2bb837","thumbnail_AppliedWebLogoEnglish102021.jpg",4.69,87,"Applied_Web_Logo_English102021_cd0b2bb837",11.64,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/Applied_Web_Logo_English102021_cd0b2bb837.jpg","2025-01-14T21:16:57.312Z",{"id":1334,"variation":757,"button":1608},[1609],{"id":1610,"label":761,"size":762,"color":763,"style":16,"icon":764,"iconPosition":765,"url":1611,"newWindow":8,"downloadable":16,"shape":16},103,"https://www.appliedmaterials.com/us/en.html","-221",{"id":280,"name":1614,"description":1615,"createdAt":1616,"updatedAt":1617,"publishedAt":1618,"url_path_id":1619,"logo":1620,"website":1629,"url_path":1635},"ASML","\u003Cp style=\"text-align:justify;\">As one of the world’s leading manufacturers of chip-making equipment, ASML provides its customers with tools - hardware, software and services - to create the patterns that define the electronic circuits on a chip. As we improve our products, our customers can increase the value and reduce the cost of chips for their customers.\u003C/p>\u003Cp style=\"text-align:justify;\">We are a global company with over 40,000 employees. Our thousands of engineers work in multi-disciplinary teams and with a network of suppliers and technology partners, innovating to maintain our technology leadership. We set ourselves ambitious goals and take pride in the impact we have on the world around us.\u003C/p>","2025-01-21T16:28:06.652Z","2025-01-21T16:28:08.471Z","2025-01-21T16:28:08.464Z","346",{"id":1621,"name":1622,"alternativeText":16,"caption":16,"width":1623,"height":1624,"formats":16,"hash":1625,"ext":33,"mime":34,"size":1626,"url":1627,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1628,"updatedAt":1628},266,"ASML_Holding_N.V._logo (1).svg",1065,300,"ASML_Holding_N_V_logo_1_85c2099fcf",3.33,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/ASML_Holding_N_V_logo_1_85c2099fcf.svg","2025-01-21T16:28:04.069Z",{"id":1630,"variation":757,"button":1631},86,[1632],{"id":1633,"label":761,"size":762,"color":763,"style":16,"icon":764,"iconPosition":765,"url":1634,"newWindow":8,"downloadable":16,"shape":16},104,"https://www.asml.com/","-222",{"pagination":1637},{"page":5,"pageSize":280,"pageCount":47,"total":554},{"id":273,"heading":316,"pageHeader":1639,"sections":1641},{"id":273,"description":1640,"showPageHeader":8,"backgroundColor":49,"image":16},"Pioneering the Future: Intelligent Compute Technologies from Materials to AI Systems",[1642],{"id":80,"__component":1643,"componentVariation":1644,"contactsVariation":1645,"styles":16,"header":16,"sessionsGroup":1646},"content.sessions","Sessions Base","Card Contact Full",[1647,1764],{"id":80,"groupTitle":1648,"sessions":1649},"Monday | May 26, 2025 | 10:00 - 11:30 ",[1650,1688,1723],{"id":448,"session":1651},{"id":252,"title":1652,"teaser":1653,"body":44,"createdAt":1654,"updatedAt":1655,"publishedAt":1656,"url_path_id":1657,"contacts":1658,"url_path":1687},"Advancing Humanity through Industry-University-IEEE partnership","\u003Cp style=\"text-align:justify;\">Industry-university-IEEE forms a symbiotic relationship. Universities train student brains while industries employ them and IEEE-like organizations give them opportunities to strive in the external world away from their industries or regular profession. IEEE strives for humanity and therefore this symbiotic relationship tries to help for the betterment of society. This talk covers efforts on how IEEE and Circuit and Systems Society (CAS) are exploring industry participation in many society activities, leading practical ways, student mentorship, internship, training, and hiring of students. This talk will summarize the attempts made through various activities in and outside of the US to have meaningful collaboration with industry-university and IEEE. Great opportunities exist through the SRC and JUMP programs which are directly connected to industry universities. Many outreach programs are related to IEEE/society activities. Examples of such successful activities as well as planned future activities this year will be given in this talk.  All these examples indicate that the role of industry-university and IEEE is critical in advancing science and technology.\u003C/p>","2025-01-23T18:41:52.300Z","2025-02-19T14:01:31.302Z","2025-01-23T18:41:54.225Z","352",[1659],{"id":1660,"name":1661,"committee":1662,"position":16,"affiliation":1663,"email":16,"biography":1664,"createdAt":1665,"updatedAt":1666,"url_path_id":1667,"contactPhoto":1668,"socialLinks":1682,"url_path":1686},176,"Rajiv Joshi","Special Panels/Industry Sessions Co-Chair","IBM, USA","\u003Cp style=\"text-align:justify;\">Dr. Rajiv V. Joshi is an IEEE Fellow, winner of the prestigious IEEE Daniel Noble award, and a key technical lead/Research Scientist at T. J. Watson Research Center, IBM. He received his B. Tech IIT (Bombay, India), M.S (MIT), and Dr. Eng. Sc. (Columbia University). He has successfully led innovations in technology, memories (SRAM, DRAM, and others), and predictive analytic techniques for yield prediction for IBM Server Groups and their products along with Compute-In-Memory and Quantum Computing. He has over 300 US patents (over 435 international patents). He has authored and co-authored over 240 refereed papers and over 70 keynote/invited papers. He is a Distinguished visiting professor at major international universities. He serves on the executive advisory committee for the Center of 3D Ferroelectric and Microelectronics at Penn State.  He is currently VP-industry of the IEEE CAS Society and CAS ambassador to India.\u003C/p>","2024-06-10T13:34:30.171Z","2025-02-19T14:33:44.374Z","241",{"id":1669,"name":1670,"alternativeText":16,"caption":16,"width":1671,"height":1671,"formats":1672,"hash":1678,"ext":781,"mime":784,"size":1679,"url":1680,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1681,"updatedAt":1681},157,"1517603161321.jpg",200,{"thumbnail":1673},{"ext":781,"url":1674,"hash":1675,"mime":784,"name":1676,"path":16,"size":1677,"width":751,"height":751},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_1517603161321_0de465ee3e.jpg","thumbnail_1517603161321_0de465ee3e","thumbnail_1517603161321.jpg",5.16,"1517603161321_0de465ee3e",7.61,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/1517603161321_0de465ee3e.jpg","2024-06-10T13:34:17.979Z",[1683],{"id":1684,"url":1685,"platform":42},658,"https://www.linkedin.com/in/rajiv-joshi-90088264/?original_referer=https%3A%2F%2Fwww.google.com%2F","-136","-226",{"id":252,"session":1689},{"id":273,"title":1690,"teaser":1691,"body":44,"createdAt":1692,"updatedAt":1693,"publishedAt":1694,"url_path_id":1695,"contacts":1696,"url_path":1722},"Materials-Device-Circuits-Systems Co-optimization for advanced logic 2nm node and beyond","\u003Cp style=\"text-align:justify;\">Systems Technology Co-optimization (STCO) and Design Technology Co-optimization (DTCO) have driven numerous logic technology innovations over many generations. As each new node introduces increased complexity and a growing number of technological advancements, it is essential to expand the traditional STCO and DTCO flows to include materials modeling. This paper demonstrates the application of a Materials-Device-Circuit-Systems Co-optimization platform by exploring various front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) technologies for the 2nm logic node and beyond. We focus on Gate-All-Around (GAA) and Complementary FET (CFET) transistors, combined with Front Side (FS) and Back Side (BS) Power Delivery Networks (PDNs). We will illustrate the impact of materials on multiple circuits, including Ring Oscillators, SRAM, and larger systems such as CPU and AI accelerators.\u003C/p>","2025-01-23T18:42:14.063Z","2025-02-19T14:34:03.557Z","2025-01-23T18:42:15.751Z","353",[1697],{"id":1698,"name":1699,"committee":16,"position":16,"affiliation":1580,"email":16,"biography":1700,"createdAt":1701,"updatedAt":1702,"url_path_id":1703,"contactPhoto":1704,"socialLinks":1717,"url_path":1721},226,"Gaurav Thareja","\u003Cp style=\"text-align:justify;\">Gaurav Thareja is Head of Logic and Memory Process Integration in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA. With a prolific career, he has made significant contributions to semiconductor device processes and materials technology. He is a recognized inventor, holding 40+ US patents, and having authored more than 30 publications and many invited talks. He received PhD in Electrical Engineering from Stanford University and has over 15 years of experience in the semiconductor industry, previously as founding team and COO of an AI startup, Process integration lead for High performance logic for 7/3/2nm nodes at Intel Process Technology Development, Design engineer for transistor reliability CAD at Texas Instruments, and internship for ROM circuit design at ST Microelectronics.\u003C/p>","2025-01-23T18:39:08.691Z","2025-02-19T14:34:23.183Z","349",{"id":1705,"name":1706,"alternativeText":16,"caption":16,"width":1671,"height":1671,"formats":1707,"hash":1713,"ext":781,"mime":784,"size":1714,"url":1715,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1716,"updatedAt":1716},267,"1708174301628.jpg",{"thumbnail":1708},{"ext":781,"url":1709,"hash":1710,"mime":784,"name":1711,"path":16,"size":1712,"width":751,"height":751},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_1708174301628_4ad70ffdfe.jpg","thumbnail_1708174301628_4ad70ffdfe","thumbnail_1708174301628.jpg",5.06,"1708174301628_4ad70ffdfe",7.59,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/1708174301628_4ad70ffdfe.jpg","2025-01-23T18:38:57.235Z",[1718],{"id":1719,"url":1720,"platform":42},699,"https://www.linkedin.com/in/gthareja","-223","-227",{"id":273,"session":1724},{"id":295,"title":1725,"teaser":1726,"body":44,"createdAt":1727,"updatedAt":1728,"publishedAt":1729,"url_path_id":1730,"contacts":1731,"url_path":1763},"DTCO/STCO exploration of new uses of the backside of chips","\u003Cp style=\"text-align:justify;\">With the advent of backside power distribution, a very interesting, new domain of possibilities is opening up, enabling a much wider set of uses of the chip backside, beyond power distribution, such as using the chip backside for signal interconnect, enabling even connections to gates directly from the backside. I’ll show some DTCO (Design-Technology Co-Optimization) and STCO (Design-Technology Co-Optimization) options and their implications in the context of CFET and 3D chip stacking, and I’ll also touch upon the possibility to use the chip backside for decoupling capacitance and cooling. Finally, backside patterning necessitates wafer bonding and thinning which introduces distortions that backside lithographic patterning will have to deal with. Some ways in which these distortions and their impact on backside patterning can be managed will be discussed as well.\u003C/p>","2025-01-23T18:42:34.866Z","2025-03-11T15:12:25.599Z","2025-01-23T18:42:36.640Z","354",[1732],{"id":1733,"name":1734,"committee":16,"position":16,"affiliation":1735,"email":16,"biography":1736,"createdAt":1737,"updatedAt":1738,"url_path_id":1739,"contactPhoto":1740,"socialLinks":1758,"url_path":1762},227,"Pieter Woltgens","ASML, The Netherlands","\u003Cp style=\"text-align:justify;\">Pieter J. M. Wöltgens works as Principal Applications Scientist at ASML, Netherlands / Belgium. After his PhD, in 1994, he joined the IBM T. J. Watson Research Laboratory in Yorktown Heights, working in VLSI design on topics like logic standard cell design, EDA, DTCO, and interfaces for 3D-stacked chips. In 2013, he joined ASML, and currently works as ASML assignee at imec in Leuven, focusing on DTCO and STCO of advanced nodes and the impact on patterning, working on topics like CFET transistors, backside power, other uses of the chip backside, and 3D chip stacking.\u003C/p>","2025-01-23T18:40:06.994Z","2025-02-19T14:36:13.778Z","350",{"id":1741,"name":1742,"alternativeText":16,"caption":16,"width":1270,"height":1270,"formats":1743,"hash":1754,"ext":19,"mime":20,"size":1755,"url":1756,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1757,"updatedAt":1757},268,"Pieter-Woeltgens.png",{"small":1744,"thumbnail":1749},{"ext":19,"url":1745,"hash":1746,"mime":20,"name":1747,"path":16,"size":1748,"width":736,"height":736},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/small_Pieter_Woeltgens_2f08efd542.png","small_Pieter_Woeltgens_2f08efd542","small_Pieter-Woeltgens.png",21.55,{"ext":19,"url":1750,"hash":1751,"mime":20,"name":1752,"path":16,"size":1753,"width":751,"height":751},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_Pieter_Woeltgens_2f08efd542.png","thumbnail_Pieter_Woeltgens_2f08efd542","thumbnail_Pieter-Woeltgens.png",4.68,"Pieter_Woeltgens_2f08efd542",22.14,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/Pieter_Woeltgens_2f08efd542.png","2025-01-23T18:39:46.321Z",[1759],{"id":1760,"url":1761,"platform":42},700,"https://nl.linkedin.com/in/pieter-w%C3%B6ltgens-5664845","-224","-228",{"id":317,"groupTitle":1765,"sessions":1766},"Tuesday | May 27, 2025 | 9:30 - 11:00 ",[1767,1804],{"id":775,"session":1768},{"id":554,"title":1769,"teaser":1770,"body":44,"createdAt":1771,"updatedAt":1772,"publishedAt":1773,"url_path_id":1774,"contacts":1775,"url_path":1803},"Energy efficient analog-digital heterogeneous accelerators","\u003Cp style=\"text-align:justify;\">Heterogeneous accelerators leveraging analog in-memory computing (AIMC), where synaptic weights are stored in nanoscale non-volatile memory elements and computations occur in the analog or mixed-signal domain, offer a promising pathway for developing highly energy-efficient deep learning accelerators. In the first part of this talk, I will discuss recent advancements in this field, with a focus on a 64-core AIMC chip fabricated using 14nm CMOS technology and embedded phase-change memory. This chip achieves classification accuracy comparable to floating-point operations while seamlessly integrating analog and digital processing units, laying the groundwork for a heterogeneous mixed-signal architecture. In the second part, I will explore ongoing efforts to design the next generation of AIMC chips for deep learning inference, targeting applications across both edge and cloud environments.\u003C/p>","2025-01-23T18:42:53.660Z","2025-02-19T14:34:44.317Z","2025-01-23T18:42:55.507Z","355",[1776],{"id":1777,"name":1778,"committee":16,"position":16,"affiliation":1779,"email":16,"biography":1780,"createdAt":1781,"updatedAt":1782,"url_path_id":1783,"contactPhoto":1784,"socialLinks":1797,"url_path":1802},215,"Abu Sebastian","IBM Research-Zurich, Switzerland","\u003Cp>Dr. Abu Sebastian is a Distinguished Scientist and technical manager at IBM Research – Zurich. In 2015 he was awarded the European Research Council (ERC) consolidator grant and in 2020, he was awarded an ERC Proof-of-concept grant. He was an IBM Master Inventor and was named Principal and Distinguished Research Staff Member in 2018 and 2020, respectively. In 2019, he received the Ovshinsky Lectureship Award for his contributions to \"Phase-change materials for cognitive computing\". In 2023, he was conferred the title of Visiting Professor in Materials by University of Oxford. He is a distinguished lecturer and fellow of the IEEE.\u003C/p>","2024-12-20T16:03:12.177Z","2025-02-19T14:35:02.159Z","323",{"id":1785,"name":1786,"alternativeText":16,"caption":16,"width":1496,"height":1496,"formats":1787,"hash":1793,"ext":781,"mime":784,"size":1794,"url":1795,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1796,"updatedAt":1796},250,"Abu Sebastian.jpg",{"thumbnail":1788},{"ext":781,"url":1789,"hash":1790,"mime":784,"name":1791,"path":16,"size":1792,"width":751,"height":751},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_Abu_Sebastian_74be26f4d1.jpg","thumbnail_Abu_Sebastian_74be26f4d1","thumbnail_Abu Sebastian.jpg",4.96,"Abu_Sebastian_74be26f4d1",11.78,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/Abu_Sebastian_74be26f4d1.jpg","2024-12-20T16:02:49.070Z",[1798],{"id":1799,"url":1800,"platform":1801},692,"https://research.ibm.com/people/abu-sebastian","Website","-201","-229",{"id":395,"session":1805},{"id":342,"title":1806,"teaser":1807,"body":44,"createdAt":1808,"updatedAt":1809,"publishedAt":1810,"url_path_id":1811,"contacts":1812,"url_path":1861},"Chips for AI and AI for Chips","\u003Cp style=\"text-align:justify;\">AI is revolutionizing the design of digital chips by automating complex tasks in Place-and-Route (PnR), Static Timing Analysis (STA), and signoff, which allows for a shift-left approach to accelerate design cycles. Predictive models optimize floorplanning, congestion management, and timing closure while EDA tools using AI optimize power, performance, and manufacturability. Predictive and generative AI are changing the face of RTL-to-GDS automation, thereby reducing iterations and increasing efficiency. This session explores cutting-edge AI methodologies in digital design, highlighting their role in faster convergence, better yield, and next-generation semiconductor development. Join us to discover how AI is reshaping the future of chip design.\u003C/p>","2025-01-23T18:43:10.575Z","2025-02-19T14:35:22.881Z","2025-01-23T18:43:12.450Z","356",[1813],{"id":1814,"name":1815,"committee":16,"position":16,"affiliation":1816,"email":16,"biography":1817,"createdAt":1818,"updatedAt":1819,"url_path_id":1820,"contactPhoto":1821,"socialLinks":1856,"url_path":1860},228,"Ayan Datta","Sandisk","\u003Cp style=\"text-align:justify;\">Ayan has an overall ~16+ years of industry experience in the VLSI domain. \u003C/p>\u003Cp style=\"text-align:justify;\">He is currently working as a technologist in Sandisk, where he is spearheading the next-gen methodology development team, which works on developing advanced digital design methodology on Ultra Deep Submicron nodes. Before joining Sandisk, he lead the timing convergence of digital design in High-Performance Intel Cores. He also led the development of several PPA design optimization tools, which were deployed across multiple projects at Intel. Before joining Intel he worked in IBM Labs for 8 years on high-performance processors designs after completing his master's degree from Jadavpur University, Kolkata. He is a Senior IEEE member and has close to 13 Publications in Leading IEEE conferences/journals and 6 US Patents. He is currently the Vice Chair of Industry Engagement of the IEEE CAS Bangalore Section.   He has been part of several organizing conference committees, including VLSID, and also chaired many sessions at conferences. \u003C/p>","2025-01-23T18:41:29.063Z","2025-04-15T14:38:15.495Z","351",{"id":1822,"name":1823,"alternativeText":16,"caption":16,"width":1824,"height":1825,"formats":1826,"hash":1851,"ext":781,"mime":784,"size":1852,"url":1853,"previewUrl":16,"provider":23,"provider_metadata":16,"createdAt":1854,"updatedAt":1855},303,"Ayan pic 2022.jpg",1878,1776,{"large":1827,"small":1833,"medium":1839,"thumbnail":1845},{"ext":781,"url":1828,"hash":1829,"mime":784,"name":1830,"path":16,"size":1831,"width":787,"height":1832},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/large_Ayan_pic_2022_60ee7b4f90.jpg","large_Ayan_pic_2022_60ee7b4f90","large_Ayan pic 2022.jpg",69.17,946,{"ext":781,"url":1834,"hash":1835,"mime":784,"name":1836,"path":16,"size":1837,"width":736,"height":1838},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/small_Ayan_pic_2022_60ee7b4f90.jpg","small_Ayan_pic_2022_60ee7b4f90","small_Ayan pic 2022.jpg",21.45,473,{"ext":781,"url":1840,"hash":1841,"mime":784,"name":1842,"path":16,"size":1843,"width":743,"height":1844},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/medium_Ayan_pic_2022_60ee7b4f90.jpg","medium_Ayan_pic_2022_60ee7b4f90","medium_Ayan pic 2022.jpg",41.77,709,{"ext":781,"url":1846,"hash":1847,"mime":784,"name":1848,"path":16,"size":1849,"width":1850,"height":751},"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/thumbnail_Ayan_pic_2022_60ee7b4f90.jpg","thumbnail_Ayan_pic_2022_60ee7b4f90","thumbnail_Ayan pic 2022.jpg",4.24,164,"Ayan_pic_2022_60ee7b4f90",189.39,"https://confcats-siteplex.s3.us-east-1.amazonaws.com/iscas25/Ayan_pic_2022_60ee7b4f90.jpg","2025-04-14T19:41:51.408Z","2025-04-14T19:42:19.261Z",[1857],{"id":1858,"url":1859,"platform":42},701,"https://in.linkedin.com/in/ayan-datta-b7754b68","-225","-230",{"data":1863,"meta":1864},{"id":273,"heading":316,"createdAt":322,"updatedAt":323,"publishedAt":324,"url_path_id":325,"url_path":328,"contentType":78},{},1778852848907]