Industry Forum

Industry-university-IEEE forms a symbiotic relationship. Universities train student brains while industries employ them and IEEE-like organizations give them opportunities to strive in the external world away from their industries or regular profession. IEEE strives for humanity and therefore this symbiotic relationship tries to help for the betterment of society. This talk covers efforts on how IEEE and Circuit and Systems Society (CAS) are exploring industry participation in many society activities, leading practical ways, student mentorship, internship, training, and hiring of students. This talk will summarize the attempts made through various activities in and outside of the US to have meaningful collaboration with industry-university and IEEE. Great opportunities exist through the SRC and JUMP programs which are directly connected to industry universities. Many outreach programs are related to IEEE/society activities. Examples of such successful activities as well as planned future activities this year will be given in this talk.  All these examples indicate that the role of industry-university and IEEE is critical in advancing science and technology.

Systems Technology Co-optimization (STCO) and Design Technology Co-optimization (DTCO) have driven numerous logic technology innovations over many generations. As each new node introduces increased complexity and a growing number of technological advancements, it is essential to expand the traditional STCO and DTCO flows to include materials modeling. This paper demonstrates the application of a Materials-Device-Circuit-Systems Co-optimization platform by exploring various front-end-of-line (FEOL), middle-of-line (MOL), and back-end-of-line (BEOL) technologies for the 2nm logic node and beyond. We focus on Gate-All-Around (GAA) and Complementary FET (CFET) transistors, combined with Front Side (FS) and Back Side (BS) Power Delivery Networks (PDNs). We will illustrate the impact of materials on multiple circuits, including Ring Oscillators, SRAM, and larger systems such as CPU and AI accelerators.

Heterogeneous accelerators leveraging analog in-memory computing (AIMC), where synaptic weights are stored in nanoscale non-volatile memory elements and computations occur in the analog or mixed-signal domain, offer a promising pathway for developing highly energy-efficient deep learning accelerators. In the first part of this talk, I will discuss recent advancements in this field, with a focus on a 64-core AIMC chip fabricated using 14nm CMOS technology and embedded phase-change memory. This chip achieves classification accuracy comparable to floating-point operations while seamlessly integrating analog and digital processing units, laying the groundwork for a heterogeneous mixed-signal architecture. In the second part, I will explore ongoing efforts to design the next generation of AIMC chips for deep learning inference, targeting applications across both edge and cloud environments.

AI is revolutionizing the design of digital chips by automating complex tasks in Place-and-Route (PnR), Static Timing Analysis (STA), and signoff, which allows for a shift-left approach to accelerate design cycles. Predictive models optimize floorplanning, congestion management, and timing closure while EDA tools using AI optimize power, performance, and manufacturability. Predictive and generative AI are changing the face of RTL-to-GDS automation, thereby reducing iterations and increasing efficiency. This session explores cutting-edge AI methodologies in digital design, highlighting their role in faster convergence, better yield, and next-generation semiconductor development. Join us to discover how AI is reshaping the future of chip design.

With the advent of backside power distribution, a very interesting, completely new domain of possibilities is opening up, enabling a much wider set of uses of the chip backside beyond power distribution, like using the chip backside for signal interconnect, enabling even connections to gates directly from the backside. I’ll some of consider these possibilities in the context of CFET and 3D chip stacking, and I’d also like touch upon some other possible uses of the chip backside for decoupling capacitance and cooling. Finally, backside patterning necessitates wafer bonding and thinning which introduces distortions that backside lithographic patterning will have to deal with and compensate for. I’ll discuss some ways in which the distortions could be reduced and/or  compensated for.

While quantum computing is generally expected to be a paradigm-shifting technology, current estimates for the required qubits for a so-called universal, fault-tolerant quantum computer run in the (tens) of millions of coherently coupled qubits. Both the inherent difficulty of quantum computing and the required error-handling mechanisms add to (or rather: multiply into) these Gargantuan numbers. Despite recent breakthroughs, the current ‘record’ numbers of coherently coupled qubits are in the 100s – still orders of magnitude removed from the target value. Many of the current record results also use ‘lab’ based methods – developed in universities and research laboratories to target sensitive qubits but without true yield and scaling in mind. In this talk, I will argue how advanced semiconductor manufacturing techniques can be tweaked and re-purposed to speed up the required advancements, by both increasing the so-called qubit fidelity (reducing error correction overheads) and increasing the yield significantly. I will use recent breakthroughs at IMEC on realizing record-high fidelity qubits with high yield in a 300 mm CMOS fabrication line as an example of the necessary lab-to-fab transition to ensure upscaling of quantum computing hardware and control.